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loginid=zlixin@waterworld.com.cn,time=2013-06-13 09:19:07,ip=219.133.107.117,doctitle=MT3332_data_sheet_external_v0.01.pdf,company=hexing_wcx version: 0.01 release date: 2011 - 1 2 - 20 ? 2008 - 2012 mediatek inc. this document contains information that is proprietary to mediatek inc. unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited. specifications are subject to change without notice. mt 3332 g nss host - based solution data sheet m e d i
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 2 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. document revision history revision date author description 0.01 201 1 /11/ 19 loris li initial version
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 3 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. table of contents document revision history ................................ ................................ ................................ .................. 2 table of contents ................................ ................................ ................................ ................................ ... 3 1 system overview ................................ ................................ ................................ .......................... 5 1.1 general descriptions ................................ ................................ ................................ ............. 5 1.2 features ................................ ................................ ................................ ................................ 6 2 pin assignment and descriptions ................................ ................................ .............................. 7 2.1 pin assignment (top view) ................................ ................................ ................................ .... 7 2.2 pin descriptions ................................ ................................ ................................ .................... 8 3 block diagrams ................................ ................................ ................................ .......................... 12 3.1 architecture of single - chip receiver ................................ ................................ .................... 12 3.2 functional block diagram (rf part) ................................ ................................ .................... 12 4 MT3332 rf part ................................ ................................ ................................ .......................... 13 4. 1 lna/mixer ................................ ................................ ................................ ........................... 13 4.2 vco/synthesizer ................................ ................................ ................................ ................ 13 4.3 lpf ................................ ................................ ................................ ................................ .... 13 4.4 adc ................................ ................................ ................................ ................................ .... 13 5 MT3332 digital part ................................ ................................ ................................ .................... 14 5.1 boot rom ................................ ................................ ................................ ........................... 14 5.2 battery backed - up memo ry ................................ ................................ ................................ 14 5.3 smps ................................ ................................ ................................ ................................ .. 15 5.4 timer function ................................ ................................ ................................ ..................... 15 5.5 gpio in rtc domain ................................ ................................ ................................ .......... 15 5.6 low power detection ................................ ................................ ................................ ........... 15 5.7 clock module ................................ ................................ ................................ ...................... 15 5.8 reset contr oller ................................ ................................ ................................ .................. 15 5.9 host interface ................................ ................................ ................................ ..................... 16 5.9.1 uart ................................ ................................ ................................ ...................... 17 5.9.2 spi ................................ ................................ ................................ .......................... 17 5.9.3 i2c ................................ ................................ ................................ ........................... 17 5.10 interrupt control unit ................................ ................................ ................................ ............ 17 5.11 gpio unit ................................ ................................ ................................ ............................ 17 5.12 pps ................................ ................................ ................................ ................................ ..... 17 5.13 eclk ................................ ................................ ................................ ................................ .. 18 5.14 sync ................................ ................................ ................................ ................................ .. 18 5.15 power scheme ................................ ................................ ................................ .................... 18 6 electrical characteristics ................................ ................................ ................................ .......... 22 6.1 dc characteristics ................................ ................................ ................................ .............. 22 6.1.1 absolute maximum ratings ................................ ................................ ...................... 22 6.1.2 recommended operating conditions ................................ ................................ ...... 22 me dia tek co nfid enti al a
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 4 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. 6.1.3 g eneral dc characteristics ................................ ................................ ..................... 23 6.1.4 dc electrical characteristics for 2.8 volts operation ................................ ................ 23 6.1.5 dc electrical characteristics for 1.8 volts operation ................................ ................ 23 6.1.6 dc electrical characteristics for 1.1 volts operation (for force_on and 32k_out) ................................ ................................ ................................ ................................ 24 6.2 analog related characteristics ................................ ................................ ............................ 24 6.2.1 smps dc characteristics ................................ ................................ ........................ 24 6.2.2 tcxo ldo dc characteristics ................................ ................................ ............... 24 6.2.3 tcxo switch dc characteristics ................................ ................................ ........ 25 6.2.4 1.1 volts core ldo dc characteristics ................................ ................................ .... 25 6.2.5 1. 1 volts rtc ldo dc characteristics ................................ ................................ ... 25 6.2.6 32 khz crystal oscillator (xosc32) ................................ ................................ ........ 25 6.3 rf related characteristics ................................ ................................ ................................ ... 26 6.3.1 dc electrical characteristics for rf part ................................ ................................ . 26 6.3.2 rx chain (gps - only) ................................ ................................ ........................... 26 6.3.3 rx chain (gps+beidou mode) ................................ ................................ ............ 27 6.3.4 rx chain (gps+glonass mode) ................................ ................................ ......... 28 6.3.5 crystal oscillator (xo) ................................ ................................ ............................. 29 7 interface characteristics ................................ ................................ ................................ ........... 30 7.1 rs - 232 interface timing ................................ ................................ ................................ ...... 30 7.2 spi interface ti ming ................................ ................................ ................................ ............ 30 7.3 i2c interface timing ................................ ................................ ................................ ............. 31 8 package description ................................ ................................ ................................ .................. 32 8.1 top mark ................................ ................................ ................................ ............................. 32 8.2 package dimensions ................................ ................................ ................................ .......... 33 lists of figures figure 3 - 1: MT3332 system block diagram ................................ ................................ ........................... 12 figure 3 - 2: MT3332 rf functional block diagram ................................ ................................ ................. 12 figure 5 - 1: rtc with internal rtc ldo application circuit 1 ................................ ................................ 14 figure 5 - 2: rtc with internal rtc ldo application circuit 2 ................................ ................................ 14 figure 5 - 3: power on reset diagram ................................ ................................ ................................ ..... 16 figure 5 - 4: power on/off reset behavior ................................ ................................ ................................ 16 figure 5 - 5: flow diagram of sync function ................................ ................................ ......................... 18 figure 5 - 6: power s upply connection (low power) ................................ ................................ ................ 19 figure 5 - 7: power supply connection (low cost) ................................ ................................ ................... 20 figure 5 - 8: power supply connection (external ldo) ................................ ................................ ........... 20 figure 5 - 9: power on/off sequence for external ldo mode ................................ ................................ . 21 figure 7 - 1: timing diagram of rs - 232 interface ................................ ................................ ................... 30 figure 7 - 2: timing diagram of spi interface ................................ ................................ ......................... 31 figure 7 - 3: timing diagram of host i2c interface ................................ ................................ ............... 31
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 5 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. 1 system overview 1.1 general d escription s mt 3332 is a high - performance single - chip gps solution which includes on - chip cmos rf and digital baseband. it is able to achieve the industrys highest level of sensitivity, accuracy and time - to - first - fix (ttff) with the lowes t power consumption in a small - footprint lead - free package. its small footprint and minimal bom requirement provide significant reductions in the design, manufacturing and testing resource required for portable applications. with built - in lna to reach tot al nf to tbd db, you can eliminate antenna requirement and do n o t need external lna. with its on - chip image - rejection mixer, the spec of external saw filter is alleviated. with an on - chip automatic center frequency calibration band pass filter, an external filter is not required. the o n - chip power management design allows mt 3332 to be easily integrated into your system without extra voltage regulator. with both linear and a high ly efficient switching type regulator embedded, mt 3332 allows direct battery con nection and does no t need any external ldo , which gives customers plenty of choices for the application circuit. up to 12 multi - tone active interference canceller s (isscc2011 award) offer you more flexibility in system design. the integrated pll with volt age controlled oscillator (vco) provides excellent phase noise performance and fast locking time. a battery back ed - up memory and a real - time clock are also provided to accelerate acquisition at the system restart - up. mt 3332 supports up to 210 prn channels . with 99 search channels and 33 simultaneous tracking channels, mt 3332 acquires and tracks satellites in the shortest time even at indoor signal levels. mt 3332 supports various location and navigation applications, including autonomous gps , glonass , gali leo, beidou(after icd released) , sbas ranging ( waas, egnos, gagan, and msas ), qzss, dgps (rtcm) and agps. through mt 3332 's excellent low - power consumption characteristic (acquisition tbd mw , track tbd mw), power sensitive devices, especially portable appl ications, you will not need to worry about the operating time anymore and can have more fun. combined with many advanced features including alwayslocate tm , easy tm , hotstill tm , epo tm and logger function, mt 3332 provides always - on position with minimal avera ge power consumption. the great features provide you supreme experience s for portable applications such as dsc, cellular phone, pmp , and gaming devices.
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 6 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. 1.2 features ? specification s ? 33 tracking / 99 acquisition - channel gps /glonass/galileo /beidou receiver ? sup port s up to 210 prn channels ? support s multi - gnss incl . qzss, sbas ranging ? supports waas/egnos/msas/gagan ? 12 multi - tone active interference canceller s (isscc2011 award) ? rtcm ready ? indoor and outdoor multi - path detection and compensation ? supports fcc e911 co mpliance and a - gps ? max . fix ed update rate up to 10 hz ? advanced software features ? alwayslocate tm advanced location awareness technology ? epo tm /hotstill tm orbit prediction ? reference o scillator ? tc xo ? frequency: 16.368 mhz, 12.6 ~ 40.0 mhz ? frequency variation: 2 . 5 ppm ? crystal ? frequency: 26 mhz, 12.6 ~ 40.0 mhz ? frequency accuracy : 10 ppm ? rf c onfiguration ? soc, integrated in single chip with cmos process ? pulse - per - second (pps) gps time reference ? adjus table d uty cycle ? typical accuracy: 10 ns ? power s cheme ? a 1.8 volts smps build - in soc ? direct lithium battery connection (2.8 ~ 4.3 volts ) ? self build 1. 1 volts rtc ldo, 1. 1 volts core ldo, and 2.8 volts tcxo ldo ? build - in reset controller ? does not n eed of ext ernal reset control ic ? internal r eal - t ime c lock (rtc) ? 32.768 k hz 20 ppm crystal ? 1. 1 volts rtc clock output ? support s external pin to wake up mt 3332 ? serial interface ? 3 uarts ? spi ? i2c ? gpio interface (up to 16 pins) ? superior sensitivities ? acquisition: - 148 dbm ( c old) / - 163 dbm ( h ot) ? tracking: - 165 dbm ? ultra - low power consumption (gps only / gps+glonass) ? acquisition: tbd/tbd mw ? tracking: tbd/tbd mw ? alwayslocate tm : tbd/tbd mw ? pack age ? qfn: 6mm x 6mm, 48 ball ? slim hardware design ? 9 passive external component s ? single rf front - end for multi - gnss frequency bands ? compatibility ? pin - to - pin compatible to mt333 6 m e d i a t e k c o n f i d e n t i a l a
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 7 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. 2 pin assignment and description s 2.1 pin a ssignment ( t op v iew)
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 8 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. 2.2 pin d escription s pin # symbol type description system i nterface (2 pins) 47 hrst_b 2.8 v lvttl input default pull - up, smt system reset. active low 46 xtest 2.8 v lvttl input default pull - down , smt test mode. must keep low in normal mode. peripheral i nterface (8 pins) 35 rx0/mm_i2cc/h_spi_si 2.8 v , lvttl i/o ppu, ppd, smt 4ma, 8ma, 12ma, 16ma pdr serial input for uart 0 default : pull - up default : 8ma driving 37 tx0/mm_i2cd/h_spi_so 2.8 v , lvttl i/o ppu, ppd, s mt 4ma, 8ma, 12ma, 16ma pdr serial output for uart 0 default : pull - up default : 8 m a driving 27 rx1/h_spi_sck/ cts0/mm_ i2cc/cxo_tsens /gio0 2.8 v , lvttl i/o ppu, ppd, smt 4ma, 8ma, 12ma, 16ma pdr serial input for uart 1 default : pull - up default : 8ma drivin g 25 tx1/txind/ rts0/mm_i2cd/ cxo_cs /gio1 2.8 v , lvttl i/o ppu, ppd, smt 4ma, 8ma, 12ma, 16ma pdr serial output for uart 1 default : pull - up default : 8ma driving 32 rx2/spi_si/jdi/dbg_rx/bs i_ck /gio2 2.8 v , lvttl i/o ppu, ppd, smt 4ma, 8ma, 12ma, 16ma pdr serial input for uart 2 default : pull - up default : 8ma driving 28 tx2/spi_so /dbg_tx /gio3 2.8 v , lvttl i/o ppu, ppd, smt 4ma, 8ma, 12ma, 16ma pdr serial output for uart 2 default : pull - up default : 8ma driving strap pin t cxo _sw_sel 1b0: avdd_t cxo _sw outp ut 1.8v 1b1: avdd_t cxo _sw output 2.8v 31 sck1/spi_sck /gio4 2.8 v , lvttl i/o ppu, ppd, smt 4ma, 8ma, 12ma, 16ma pdr spi clock output default : pull - up default : 8ma driving strap pin clk_sel[0] clk_sel[1:0] mode 2b00: xtal mode 2b01: external clock mode 2b10: tc xo mode 2b11: 16.368mhz tcxo mode
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 9 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. pin # symbol type description 41 scs1#/spi_scs#/bsi_dat a /sync_pulse /gio5 2.8 v , lvttl i/o ppu, ppd, smt 4ma, 8ma, 12ma, 16ma pdr spi slave select ion 1 default : pull - up default : 8ma driving strap pin clk_sel[1] debug ging i nterface (6 pins) 26 bsi_ck/mm_i2cc/eclk /gi o6 2.8 v , lvttl i/o ppu, ppd, smt 4ma, 8ma, 12ma, 16ma pdr gpio6 default : pull - down default : 8ma driving 40 bsi_cs/mm_i2cd/duty_c ycle/pps /gio7 2.8 v , lvttl i/o ppu, ppd, smt 4ma, 8ma, 12ma, 16ma pdr gpio7 default : pull - down defa ult : 8ma driving 33 frame_sync/dbg_rx /gi o8 2.8 v , lvttl i/o ppu, ppd, smt 4ma, 8ma, 12ma, 16ma pdr gpio8 . default : pull - down default : 8ma driving 39 pps/dbg_tx /gio9 2.8 v , lvttl i/o ppu, ppd, smt 4ma, 8ma, 12ma, 16ma pdr gpio9 default : pull - up defa ult : 8ma driving strap pin host_sel[0] host_sel[1:0] interface 2b00: i2c 2b01: uart meif 2b10: spi 2b11: uart 34 cxo_cs /gio10 2.8 v , lvttl i/o ppu, ppd, smt 4ma, 8ma, 12ma, 16ma pdr gpio10 default : pull - up default : 8ma driving strap pin host_sel[ 1] 38 h_spi_scs#/cxo_tsens/ sync_pulse /gio11 2.8 v , lvttl i/o ppu, ppd, smt 4ma, 8ma, 12ma, 16ma pdr gpio11 default : pull - up default : 8ma driving external s ystem i nterface ( 3 pins) 44 eint0/mm_i2cc/bsi_cs /gi o12 2.8 v , lvttl i/o ppu, ppd, smt 4ma, 8ma , 12ma, 16ma pdr external interrupt 0 default : pull - down default : 8ma driving 45 eint1/mm_i2cd/pps/bsi_d ata /gio13 2.8 v , lvttl i/o ppu, ppd, smt 4ma, 8ma, 12ma, 16ma pdr external interrupt 1 default : pull - down default : 8ma driving 36 eint2/dbg_rx/pps /gio1 4 2.8 v , lvttl i/o ppu, ppd, smt 4ma, 8ma, 12ma, 16ma pdr external interrupt 2 default : pull - up default : 8ma driving rtc i nterface (6 pins)
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 10 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. pin # symbol type description 19 avdd43_rtc analog power rtc ldo input 18 avdd1 1 _rtc analog power rtc ldo output 21 xin analog input rtc 32 k hz xtal input 20 xout analog output rtc 32 k hz xtal output 23 32k_out/dr_in 1.2 v lvttl i/o ppu, ppd, smt 4ma, 8ma, 12ma, 16ma pdr rtc domain gpio pin, can be programmed to 32 k hz clock output or dr wake - up signal input default : 75k pull - down default : 16ma driving 22 force_on 1.2 v lvttl i/o ppu,ppd , smt force to power on this chip . rf & a nalog 1 avdd 18 _ rxfe rf p ower 1.8 v supply for rf core circuits 2 t1p analog signal rf testing signal 3 t1n analog signal rf testing signal 4 avdd 18 _ cm rf power 1.8v supply for xtal osc, bandgap, thermal sensor and level shifter 5 o sc analog signal input for crystal oscillator or tcxo 48 rf _ in rf signal lna rf input pin 6 dvdd 11 _core1 digital power digital 1. 1 v core power input 24 dvdd 11 _core2 digital power digital 1. 1v core power input 43 dvdd 11 _core 3 digital power digital 1. 1 v core power input 30 dvdd 28 _io1 digital power digital 1.8/2.8 v io power input 42 dvdd 28 _io2 digital power digital 1.8/2.8 v io power input 29 gnd digital ground digital ground 7 vref analog bandgap output pin. must add 1uf decoupling cap on evb. 8 avss43_ misc analog ground gnd pin for buck controller , tcxo ldo and start - up block 9 avdd43_vbat analog power tcxo ldo input pin. always be powered by external source. uvlo will detect this pin to check power status. 10 avdd_t cxo _sw analog power tcxo power switch output pin 11 avdd 28_tldo analog power tcxo ldo output pin 12 avdd28_cldo analog power core ldo input pin. a lways powered by external source or smps 13 avdd1 1 _cldo analog power core ldo output pin 14 avss43 _ dcv smps smps g nd pin 15 dcv smps smps output pin 16 avdd43_ dcv smps smps input pin. 17 dcv _fb smps smps feedback pin note s: ppu = programmable pull - up ppd = programmable pull - down psr = programmable slew rate
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 11 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. pdr = programmable driving
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 12 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. 3 block diagrams 3.1 architecture o f s ingle - c hip r eceiver figure 3 - 1 : mt 3332 s ystem b lock d iagram 3.2 functional b lock d iagram (rf p art) figure 3 - 2 : mt 3332 rf f unction al b lock d iagram a d c a n t e n n a d e t e c t o r p f d c p x o s c l n a p g a i f f i l t e r v c o ( 2 x l o ) 4 b i t 2 s d m r f l d o ( ) ( 1 . 5 ) a d c p f d c p x o s c l n a i f f i l t e r v c o ( 2 x l o ) 2 m m d + s d m r f l d o 2 2 m i x e r b g / 2 4
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 13 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. 4 mt 3332 rf part 4.1 lna/mixer upon receiving rf input signal in through either gps antenna to internal lna or external antenna and lna, the mixer down converts the amplified signal (gps/galileo=1575.42mhz, beidou=1561.098 - mhz, glonass=1601.71 - mhz). the current chip provides 2 configurations to choose from, which are high - gain lna and low - gain lna. the h igh - gain lna is used for low - cost solution without external lna. the l ow - gain lna offers high linearity to allow high external lna gain, with mu ch worsen noise figure performance. in the application with external lna, the external lna gain ranging from 0 to 20 db is recommended. the down - conversion mixer is single - ended passive mixer with current mode interface between the mixer and multi - modes lo w pass filter. 4.2 vco/synthesizer the entire frequency synthesizer includ es crystal oscillator, vco, divider, phase frequency detector (pfd), charge pump (cp) and loop filter which are all integrated on the mt 3332 chip. upon power - on, vco is auto - calibrated t o its required sub - band. the synthesizer adopts fractional - n sigma - delta pll topology, which supports 12.6 to 40mhz reference clock frequencies. 4.3 lpf the current - mode lpf supports multiple modes for different gnss combination s . the lpf also provides 26db gain - control range, with approximately 2db per step. 4.4 adc the differential if signal is being quantized by a high performance adc. the sampling clock can be provided from divided clock from lo. the adc can be programmed between high performance mode (gps+gl onass) for high bandwidth, and low performance mode (gps - only) for lower current consumption.
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 14 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. 5 mt 3332 digital part 5.1 boot rom the embedded boot rom provides a function of loading a set of user code through the host interface into sram. the host interface (uar t/spi/i2c) is decided by strap control. 5.2 battery b acked - up m emory mt 3332 provides very low leakage (about tbd ua in the backup mode) battery backed - up memory, which contains all the necessary gps information for quick start - up and a small amount of user con figuration variables. there is a buil t - in 1. 1 volts ldo for rtc domain and it c an be bypassed while an external ldo is applied. th e rtc ldo is a voltage regulator ha ving very low quiescent current, and typical quiescent current < tbd ua . the s mall ceramic capacitor can be used as the output capacitor, and the stable operation region ranges from very light load (~=0) to about tbd ma. figure 5 - 1 : rtc with i nternal rtc ldo a pplication c ircuit 1 figure 5 - 2 : rtc with i nternal rtc ldo a pplication c ircuit 2
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 15 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. 5.3 smps a built - in switching mode power supply provides 1.8 volts power supply for the digital 1. 1 volts cldo and rf input power . i n the active mode, smps is ope rated in the pwm mode . in the power saving mode, smps is operated with reduced switching frequency in the pfm mode. the recommended l/c value is 1 uh / 4.7 uf. 5.4 timer function the timer function supports a time tick generation of 31.25 ms resolution. with t he 24 - bit counter, the period of timer is from 31.25 m s to 524 , 287 s. 5.5 gpio in rtc domain the 32k_out pin in rtc domain can output 32.768 k hz clock which can be used to support low clock rate operation mode for some applications or peripherals that need a n external clock source. this pin can also be programmed to be an input pin to receive the signal from an external a ccelerator s ensor ic to be the wake - up signal of mt 3332 when it is in the low - power mode. 5.6 low power detection a low power detection circuit is implemented . w henever the independent power source (avdd1 1 _rtc) becomes low voltage, the low power detection circuit will detect this condition and use a n indicator signal (output high in normal condition and low in low - power condition) to reflect this condition. 5.7 clock module th e clock module generates all internal clocks required by processor, correlator, internal memory, bus interface and so on. the referenced input clock is generated from the rf block. for system flexibility and maximum power saving, it supports various power management modes. 5.8 reset controller the buil t - in reset controller generate s reset signal s for all digital blocks. it has power - on reset feature and hardware trapping function. the power - on reset level is 2.7 0.1 volts . the s oftwa re reset function for different circuit blocks are also included for flexible applications . in figure 5 - 4 , the voltage drop time t drop_vbat and t drop_cldo depend on the capacitance connection of their power net. but t drop_vbat > t drop_cldo should be guaranteed for the correct operation of reset behavior during power off sequence. it is strongly recommend using external ldos without output discharged function or make sure t drop_vbat > 100 ms.
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 16 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. figure 5 - 3 : power on reset diagram figure 5 - 4 : power on /off reset behavior 5.9 host i nterface mt 3332 support s 3 different host interface s , which are uart, spi, and i2c. the interface used as the host interface is determined by strap pins. note that spi and i2c support firmware update only for now.
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 17 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. 5.9.1 uart uart is the abbreviation of universal asynchronous receiver/transmitter. mt 3332 has 3 full duplex serial ports. it is used for serial data communicati on . a uart converts bytes of data to and from asynchronous start - stop bit streams represented as binary electrical impulses. t here are several functions in mt 3332 related to uart communication, such as uart data transmission/receive and aiding information input from host processor . in general, uart0 is as measurement data output and pmtk command input , uart1 as rtcm input. you can adjust the uart2 port as desired . the receiver (rx) and transmitter (tx) side of every port contains a 16 - byte fifo , but only u art0 has 256 bytes of uram. the bit rates are selectable and rang e from 4.8 to 921.6 k bps. uart provide s signal or message outputs. 5.9.2 spi the serial peripheral interface port manages the communication between digital bb and external devices. mt 3332 supports both m aster and s lave m ode s . only 4 bytes of register in the m aster mode can be transferred. the s lave has 4 - byte - register mode or uram mode. in the uram mode, the transmit ted and receiv ed data size is 256 bytes. the clock phase and clock polarity are sele ctable. mt 3332 supports manual or automatic indicator for data transfer in the slave mode. 5.9.3 i2c the i2c interface is mainly connected to external devices. mt 3332 supports m ulti - m aster and s lave m ode s . both modes have 256 - byte uram mode and 8 - byte fifo mode for transmitting and receiving data. the multi - master mode supports 7 - bit and 10 - bit address mode s up to 400 kb/s fast mode and 3.4 mb/s high - speed mode. in additions, mt 3332 supports manual or automatic indicator for data transfer in the slave mode. d evic e addresses in the slave mode are programmable and support fast mode and high - speed mode data transmi ssion and rece ption . 5.10 interrupt c ontrol u nit the interrupt control unit manages all internal and external sources of interrupts, which include timer, watch - dog, all interface s such as uart, i2c and spi and external user interrupt pins. these interrupt sources c an be wake - up event s in the power saving mode. 5.11 gpio u nit gpio is the abbreviation of g eneral - purpose input/ o utput . mt 3332 supports a variety of perip herals through maximum 1 5 gpio programmable ports. the unit manages all gpio lines and supports a simple control interface. gpio provide s signal or message outputs. 5.12 pps the pps (pulse per second) signal is provided through designated output pin for many ex ternal applications. th e pulse is not only limited to be ing active every second but also allowed to set up the required duration, frequency and active high/low by programming user - defined settings.
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 18 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. 5.13 eclk eclk is a clock input pin for introducing an external clock signal to mt 3332 and obtaining the relation between the external clock and gps local clock. with precise external clock input, the clock drift of the gps local clock can be correctly estimated. therefore, the d oppler search range is narrowed down ac cordingly. th e technology is beneficial to speeding up the satellite acquisition process. particularly in the cold start case, due to limited prior i information about the satellites location and local clock uncertainty, a receiver w ill execute a search in full frequency range. consequently, a longer acquisition time is expected. however, the eclk technology is able to reduce the frequency uncertainty so that the search process will be completed in a short time . efficient acquisition and lower power consump tion are attained by the eclk technology. 5.14 sync sync is a time stamp signal input pin for introducing an external timing to the gps receiver and obtaining the relation between the external timing and the gps receiver local timing. with precise external timi ng input and the established relation, the gps time of week (tow) can be correctly estimated in the gps receiver. th e technology is beneficial for time to first fix (ttff), particularly in weak signal environments. in hot start s , with priori information ab out the gps receivers location and satellite ephemeris data, the gps receiver uses the correct gps tow to accurately predict the signal code chip/phase. therefore, the code search range can be narrowed down accordingly. hence, fast ttff is achieved by the sync technology. figure 5 - 5 : flow diagram of sync f unction 5.15 power s cheme ? internal smps is used as the source power of the internal rf/bb ldo . it is also used as 1.8 volts i / o power. the i nternal smps can switch to the ldo mode to supply power to each of the about block ? external ldo or vbat can be used as the main power. the m inimum/ m aximum input voltage of avdd43_vbat and avdd43_ dcv is 2.8/4.3 volts . ? the p ower - on reset voltage threshold of avdd43_vbat is 2 .7 0.1 volts . the m ax imum tldo drop out voltage at half load ( 25 ma ) is 0.25 volts . if one external ldo is used to provide power to
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 19 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. mt 3332 , the 3. 3 volts external ldo will be recommended after taking tldo drop - out into consideration. ? t he power efficienc y in smps mode will be better than that in the internal ldo mode . ? i / o support s 1.8 and 2.8 volts . the power comes from smps output for 1.8 volts application or tldo output (avdd28_tldo) for 2.8 volts application. ? tcxo power is from avdd_t cxo _sw with an int ernal mux to select 2.8 volts from avdd28_tldo or 1.8 volts from avdd28_cldo by setting up power - on strap. ? rtc ldo input power comes f rom avdd28_tldo and use s coin battery as the backup battery. a scho t tky diode is usually used to avoid leakage from coin b attery to tldo. ? here are 3 power schemes : low power ( figure 5 - 6 ) , low cost ( figure 5 - 7 ) and external pmu ( figure 5 - 8 ) . ? in figure 5 - 8 , if 2.8 v tcxo is used, avdd28_cldo should be open for sav ing power. figure 5 - 6 : power s upply c onnection ( l ow p ower)
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 20 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. figure 5 - 7 : power s upply c onnection ( l ow c ost) figure 5 - 8 : power s upply c onnection ( e xternal ldo)
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 21 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. figure 5 - 9 : power on/off sequence for e xternal ldo mode
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 22 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. 6 electrical characteristics 6.1 dc characteristics 6.1.1 absolute maximum ratings s ymbol p arameter r ating u nit avdd43_ dcv smps p ower s upply - 0.3 ~ 4.3 v avdd43_vbat 2.8 volts tldo p ower s upply - 0.3 ~ 4.3 v avdd28_cldo 1. 1 volts cldo p ower s upply - 0.3 ~ 3. 6 v dvdd 28 _io1 dvdd 28 _io2 io 2.8/1.8 volts p ower s upply - 0.3 ~ 3.6 v dvdd 11 _core1 dvdd 11 _core2 dvdd11_core3 baseband 1. 1 volts p ower s upply - 0.3 ~ 1.21 v avdd43_rtc rtc 1. 1 volts ldo p ower s upply - 0.3 ~ 4.3 v avdd 18 _r xfe 1.8 volts supply for rf core circuits - 0.3 ~ 3. 6 v avdd 18 _ cm - 0.3 ~ 3. 6 v t stg storage t emperature - 50 ~ +125 c t a operating t emperature - 45 ~ +85 c 6.1.2 recommended o perating c onditions s ymbol p arameter m in. t yp. m ax. u nit avdd43_ dcv smps p ower s upply 2.8 3.3 4.3 v avdd43_vbat 2.8 volts tldo p ower s upply 2.8 3.3 4.3 v dvdd 11 _core1 dvdd 11 _core2 dvdd11_core3 1. 1 volts b aseband c ore p ower 0.99 1. 1 1.2 1 v dvdd 28 _io1 dvdd 28 _io2 2.8 volts digital i / o power 2.52 2.8 3.08 v 1.8 volts digital i / o power 1.62 1.8 1.98 v avdd 18 _r xfe 1 . 35 volts supply for rf core circuits in bypass mode 1. 3 1. 35 1. 98 v 1.8 volts supply for rf core circuits in ldo mode 1.62 1.8 3.08 v avdd18_cm 1.35 volts supply for common rf block in bypass mode 1.3 1.35 1.98 v 1.8v volts supply for common rf block in ldo mode 1.62 1.8 3.08 v t a t j operating temperature - 40 25 85 c commercial j unction o perating t emperature 0 25 115 c industry j unction o perating t emperature - 40 25 125 c
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 23 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. 6.1.3 general dc c haracteristic s s ymbol p arameter c ondition m in. m ax. u nit i il input low current no pull - up or down - 1 1 ua i ih input high current no pull - up or down - 1 1 ua i oz tri - state leakage current - 10 10 ua 6.1.4 dc e lectrical c haracteristics for 2.8 v olts o peration symbol parameter condition min. typ . max. unit vdd supply voltage of core pow e r 0.99 1.1 1.21 v vddio supply voltage of io power 2.52 2.8 3.08 v v il input lower voltage lvttl - 0.3 - 0.25*vddio v v ih input high voltage 0.75*vddio - vddio+0.3 v v ol output low voltage vddio = min i ol = - 2 ma - - 0.15*vddio v v oh output high voltage vddio = min i oh = - 2 ma 0.85*vddio - - v r pu input pull - up resistance vddio = typ vinput = 0 v 40 85 190 k r pd input pull - down resistance vddio = typ vinput = 2.8 v 40 85 190 k 6.1.5 dc e lectrical c haracteristics for 1.8 v olts o per ation symbol parameter condition min. typ . max. unit vdd supply voltage of core pow e r 0.99 1.1 1.21 v vddio supply voltage of io power 1.62 1.8 1.98 v v il input lower voltage lvttl - 0.3 - 0.25*vddio v v ih input high voltage 0.75*vddio - vddio+0.3 v v ol output low voltage vddio = min i ol = - 2 ma - - 0.15*vddio v v oh output high voltage vddio = min i oh = - 2 ma 0.85*vddio - - v r pu input pull - up resistance vddio = typ vinput = 0 v 70 150 320 k r pd input pull - down resistance vddio = typ vinput = 1.8 v 70 150 320 k
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 24 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. 6.1.6 dc e lectrical c haracteristics for 1. 1 v olts o peration ( f or force_on and 32k_out) symbol parameter condition min. typ . max. unit vdd supply voltage of core pow e r 0.99 1.1 1.21 v vddio supply voltage of io power 0.99 1.1 1.21 v v il input lower voltage lvttl - 0.3 - 0.25*vddio v v ih input high voltage 0.75*vddio - vddio+0.3 v v ol output low voltage vddio = min i ol = - 2 ma - - 0.15*vddio v v oh output high voltage vddio = min i o h = - 2 ma 0.85*vddio - - v r pu input pull - up resistance vddio = typ vinput = 0 v 130 560 k r pd input pull - down resistance vddio = typ vinput = 1.1 v 130 560 k 6.2 analog r elated c haracteristics 6.2.1 smps dc characteristics symbol parameter min. typ. max. unit note avdd43_ dcv smps input supply voltage 2.8 3.3 4.3 v dcv smps output 1.74 1.84 1.9 4 v i max smps current limit 120 - 500 ma i cc for normal operation current - 20 100 ma ? v_pwm ripple of pwm mode - - 40 mv w ith l= 1 uh, c= 4.7uf ? v_pfm ripple of pfm mode - - 90 mv w ith l= 1 uh, c= 4.7uf i q quiescent current - 50 65 ua 6.2.2 tcxo ldo dc char acteristics symbol parameter min. typ. max. unit note avdd43_vbat tcxo ldo input supply voltage 2.8 3.3 4.3 v w ill change to bypass mode under 3.1 volts avdd28_tldo tcxo ldo output 2.71 2.8 2.8 9 v i max tcxo ldo current limit 60 - 250 ma i cc for norm al operation current - 1 50 ma not include external devices psrr - 30 khz 35 - - db co = 1 uf, esr = 0.05, iload = 25 ma load regulation - 84 10 84 mv
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 25 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. symbol parameter min. typ. max. unit note i q quiescent current - 50 65 ua 6.2.3 tcxo switch dc characteristics symbol parameter min. typ. max. unit note avdd_t cxo _s w tcxo switch output voltage @ tcxo switch input = avdd28_tldo 2.66 - - v avdd_t cxo _s w tcxo switch output voltage @ tcxo switch input = avdd28_cldo 1.71 - - v i max tcxo switch current limit - - 30 ma 6.2.4 1. 1 volts core ldo dc character istics symbol parameter min. typ. max. unit note avdd28_cldo 1.2 volts ldo input supply voltage 1.62 1.8 3.08 v avdd1 1 _cldo 1. 1 volts ldo output 1.05 1.12 1.2 v i max 1. 1 volts ldo current limit 60 - 250 ma i cc for normal core operation current - 15 50 ma load regulation - - - mv i q quiescent current - 10 20 ua 6.2.5 1. 1 volts rtc ldo dc c haracteristic s s ymbol p arameter m in. t yp. m ax. u nit n ote avdd43_rtc rtc ldo input s upply voltage 2 4 4.3 v avdd1 1 _rtc rtc ldo output 0.9 9 1. 1 1. 21 v i max rtc ldo current limit - - - ma i cc for normal rtc operation current - - 3 ma i q quiescent current - - 3.5 ua i leak leakage current 2. 2 10 - ua including ldo and rtc domain circuit 6.2.6 32 k hz c rystal o scillator (xosc32) symbol parame ter min. typ. max. unit note avdd1 1 _rtc analog power supply 0.99 - 1. 21 v dcyc duty cycle - 50 - %
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 26 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. 6.3 rf related chara cteristics 6.3.1 dc electrical characteristics for rf part symbol parameter min. typ. max. unit i cc (gps - onlly) total supply current: - tbd tbd ma i cc (gps+galileo) total supply current: - tbd - ma i cc (gps+beidouu) total supply current: - tbd - ma i cc (gps+glonass) total supply current: - - tbd ma 6.3.2 rx chain (gps - only) parameter condition min. typ. max. unit rf input frequency - 1575.4 - mh z lo frequency lo frequency is 4.092mhz lower than rf - 1571.3 - mhz lo leakage measured at balun matching network input at lna high gain - - 70 - dbm input return loss single - ended input and external matched to 50 source using balun matching network for all gain - 10 - - db gain (av) (integrated average over fc+ - 4m) high current mode with max pga gain 80 78 76 db low current mode with max pga gain - - 58 db pga gain range - 24 - db pga gain step - 2 - db ga in compression blocker - 25dbm cw at 1710mhz, relative to uncompressed gain, max pga gain - 1 2 db nf high current mode with max pga gain - tbd - db low current mode with max pga gain - 4.8 - db nf at gain=62db relative to nf at max gain - 0.5 1 db nf at gain=52db relative to nf at max gain - 2 3 db nf under compression blocker - 25dbm cw at 1710mhz, max gain - 7 10 db input ip3, inband max gain, 5m/10m offset@ - 60dbm - 35 - 30 - dbm input ip3, outband max gain, ~2000m/2400m@ - 40dbm - 15 - 10 - dbm input ip2, outband max gain, ~800m/2400m@ - 40dbm +30 +35 - dbm input p1 db, inband pga gain=0db, offset 500 k - 58 - 55 - frequency response, relative to 4.092mhz, (gps/galileo) at offset + - 3mhz - - 12/ - 6 - at offset + - 10mhz - - 40/ - 34 - at offs et + - 20mhz - - 60/ - 54 - at offset + - 100mhz - - 100/ - 94 - gain ripple, gps 4.092+ - 1mhz - 1.0 1.5 db
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 27 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. gain ripple, galileo 4.092+ - 2mhz - 2.0 3.0 db delay ripple, gps 4.092+ - 1mhz - 60 110 ns delay ripple, galileo 4.092+ - 2mhz - 40 70 ns image rejection a ll mode - 35 - db dc offset - 50 100 mv adc clock - 16.368 - mhz adc input fs - 1.0 - vppd adc enob 7.5 8.3 - bits snr over fclk/2 45 50 - db rx current high current mode - tbd - ma low current mode - tbd - ma 6.3.3 rx chain (gps+beidou mode) pa rameter condition min. typ. max. unit rf input frequency - 1561 - mhz lo frequency lo frequency is 4.092 mhz lower than rf - 1568.2 - mhz lo leakage measured at balun matching network input at lna high gain - - 70 - dbm input return loss differential input and external matched to 50 source using balun matching network for all gain - 10 - - db gain (av) (integrated average over fc+ - 4m) high current mode with max pga gain 80 76 70 db low current mode with max pga gain - - 52 db pga gain range - 24 - db pga gain step - 2 - db gain compression blocker - 25dbm cw at 1710mhz, relative to uncompressed gain, max pga gain - 1 2 db nf (integrated average over fc+ - 2m) high current mode with max pga gain - 1.7 - db low current mode with max pga gain - 4.8 - db nf at gain=56db relative to nf at max gain - 0.5 1 db nf at gain=46db relative to nf at max gain - 2 3 db nf under compression blocker - 25dbm cw at 1710mhz, max gain - 7 10 db input ip3, inband max gain, +10m/+20m offset @ - 70dbm - 50 - 45 - dbm input ip3, outband max gain, ~2000m/2400m@ - 40dbm - 15 - 10 - dbm input ip2, outband max gain, ~800m/2400m @ - 40dbm +30 +35 - dbm input p1 db, inband pga gain=0db, offset 500 k - 58 - 55 - dbm frequency response (relative to 7.16m) at 0~5mhz - 3 4 db at 33 mhz - - 43 - 40 db at 53mhz - - 60 - 57 db
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 28 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. at 120mhz - - 83 - 80 db at 180mhz - - 100 - 97 db lpf 3 db bandwidth (recom. 4 th order butterworth bw=9m) - tbd - mhz gain ripple 7.2+ - 1mhz - 0.5 1.0 db 7.2+ - 2mhz - 1.0 2.0 db delay ripple 7.2+ - 2mhz - 40 70 ns image rejection all gain mode - 35 - db dc offset - 50 100 mv adc clock - 66 - mhz adc input fs - 1.0 - vppd adc enob 7.5 8.3 - snr over fclk/2 45 50 - db rx current high current mode - tbd - ma low current mode - tbd - ma 6.3.4 rx chain (gp s+glonass mode) parameter condition min. typ. max. unit rf input frequency - 1575.4 - mhz lo frequency - 1588.6 -- mhz lo leakage measured at balun matching network input at lna high gain - - 70 - dbm input return loss differential input and external matched to 50 source using balun matching network for all gain - 10 - - db gain (av) (integrated average over fc+ - 4m) high current mode with max pga gain 80 76 70 db low current mode with max pga gain - - 52 db pga gain range - 24 - db pga gain step - 2 - db gain compression blocker - 25dbm cw at 1710mhz, relative to uncompressed gain, max pga gain - 1 2 db nf (integrated average over fc+ - 4m) high current mode with max pga gain - 1.7 - db low current mode with max pga gain - 4.8 - db nf at gain =56db relative to nf at max gain - 0.5 1 db nf at gain=46db relative to nf at max gain - 2 3 db nf under compression blocker - 25dbm cw at 1710mhz, max gain - 7 10 db input ip3, inband max gain, +10m/+20m offset@ - 70dbm - 50 - 45 - dbm input ip3, outband max gain, ~2000m/2400m@ - 40dbm - 15 - 10 - dbm input ip2, outband max gain, ~800m/2400m@ - 40dbm +30 +35 - dbm input p1 db, inband pga gain=0db, offset 500 k - 58 - 55 - dbm frequency response at 0~23mhz - 3 4 db at 33mhz - - 25 - 22 db
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 29 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. (relative to 13.14m) at 53mhz - - 43 - 40 db at 120mhz - - 66 - 63 db at 180mhz - - 85 - 82 db lpf 3 db bandwidth (recom. 4 th order butterworth bw=15m) - tbd - mhz gain ripple 13+ - 1mhz - 0.5 1.0 db 13+ - 4mhz - 2.0 3.0 db delay ripple 13+ - 4mhz - 10 14 ns image reje ction all gain mode - 35 - db dc offset - 50 100 mv adc clock - 66.192 - mhz adc input fs - 1.0 - vppd adc enob 7.5 8.3 - bits snr over fclk/2 45 50 - db rx current high current mode - tbd - ma low current mode - tbd - ma 6.3.5 crystal oscilla tor (xo) symbol parameter min. typ. max. unit f tcxo tcxo oscillation frequency 12.6 16.368 40 mhz v tcxo tcxo output swing 0.8 1.2 - vpp
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 30 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. 7 interface characteristics 7.1 rs - 232 i nterface t iming baud r ate r equired (bps) programmed b aud r ate (bps) baud r ate e rror ( %) baud r ate e rror (%) 3 4 , 800 4 , 800.000 0.0000 0.002 9 , 600 9 , 600.000 0.0000 0.002 14 , 400 14 , 408.451 0.0587 0.0567 19 , 200 19 , 164.319 0.0587 0.0567 38 , 400 38 , 422.535 0.0587 0.0567 57 , 600 57 , 633.803 0.0587 0.0567 115 , 200 115 , 267.606 0.0587 0.0567 230 , 400 230 , 535.211 0.0587 0.0567 460 , 800 454 , 666.667 - 1.3310 - 1.3330 921 , 600 909 , 333.333 - 1.3310 - 1.3330 note s : 1. uart baud - rate settings with uart_clk frequency = 16.368 mhz (uart_clk uses the reference clock of the system). 2. the baudrate error is optimized . each baudrate need s to adjust counter to obtain the optimized error. 3. s uppose tcxo frequency is exactly at 16.368 mhz. if tcxo has 20 ppm, the error will raise slightly . figure 7 - 1 : timing diagram of rs - 232 interface 7.2 spi i nterface t iming description symbol min . max . unit note scs# setup time t1 0.5t - ns 1 scs# hold time t2 0.5t - ns 1 so setup time t3 0.5t C 3t 0.5t - 2t ns 1, 2 so hold time t4 0.5t + 2t 0.5t + 3t ns 1, 2 s in setup time t5 3t - ns 1, 2 sin hold time t6 10 - ns 1 note s : s t a r t b i t e n d b i t d a t a b i t s ( o n e b y t e ) l s b t x / r x
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 31 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. 1. the condition of spi clock cycle (t) is (spi_ipllspi_ipll/12) m h z ~ (rf_clk/1 , 020) m h z. 2. t indicates the period of spi controller clock, which is spispi_ipll clock or rf_clk. figure 7 - 2 : timing diagram of spi i nterface 7.3 i2c i nterface t iming symbol period t1 (mm_cnt_phase_val0+1)/tcxo_clk t2 (mm_cnt_phase_val1+1)/tcxo_clk t3 (mm_cnt_phase_val2+1)/tcxo_clk t4 (mm_cnt_phase_val3+1)/tcxo_clk note: the condition of i2c clock cycle (i2c_clk) is (tcxo_clk/4) mhz ~ (tcxo_clk/(mm_cnt+4)) mhz. the mm_cnt is sum of mm_cnt_phase_val0, mm_cnt_phase_val1, mm_cnt_phase_val2 and mm_cnt_pha se_val3 in full speed mode. figure 7 - 3 : timing di a gram of host i2c i nterface s c k t 1 t 2 t 3 t 4 t 3 t 4 t 5 t 6 t 5 t 6 s c s # s o s i n m s b m s b l s b l s b i 2 c _ sda i 2 c _ scl t 1 t 4 t 3 t 2
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 32 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. 8 package d escription 8.1 top mark n : qfn package dddddd : date code llllll : lot number mtk mt333 2 n dddddd llllll B
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 33 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. 8.2 package dimensions
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 34 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited.
orjlqlg ]ol[lq#zdwhuzruogfrpfqwlph ls grfwlwoh 07bgdwdbvkhhwbh[whuqdobysgifrpsdq\ +h[lqjb:&; mt 3332 g nss host - based solution confidential a mediatek confidential ? 2012 mediatek inc. page 35 of 35 this document contains information that is proprietary to mediatek inc. unauthorized reprodu ction or disclosure of this information in whole or in part is strictly prohibited. esd caution mt 3332 is esd (electrostatic discharge) sensitive device and may be damaged with esd or spike voltage. although mt 3332 is with built - in esd protection circuitry, please handle with care to avoid permanent m alfunction or performance degradation. use of the gps data and services at the user's own risk the gps data and navigation services providers, system makers and integrated circuit manufactures (providers) hereby disclaim any and all guarantees, represe ntations or warranties with respect to the global positioning system (gps) data or the gps services provided herein, either expressed or implied, including but not limited to, the effectiveness, completeness, accuracy, fitness for a particular purpose or t he reliability of the gps data or services. the gps data and services are not to be used for safety of life applications, or for any other application in which the accuracy or reliability of the gps data or services could create a situation where personal injury or death may occur. any use there with are at the users own risk. the providers specifically disclaims any and all liability, including without limitation, indirect, consequential and incidental damages, that may arise in any way from the use of or reliance on the gps data or services, as well as claims or damages based on the contravention of patents, copyrights, mask work and/or other intellectual property rights. no part of this document may be copied, distributed, utilized, and transmitted in an y form or by any means without expressed authorization of all providers. the gps data and services are in part or in all subject to patent, copyright, trade secret and other intellectual property rights and protections worldwide. mediatek reserves the righ t to make change to specifications and product description without notice.

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